International Wafer-Level Packaging Conference (IWLPC) Keynote Presenters Announced

The SMTA and Chip Scale Review are pleased to announce the Keynote Presenters for the 14th annual International Wafer-Level Packaging Conference. The IWLPC will be held October 24-26, 2017 at the DoubleTree by Hilton Hotel in San Jose, California.

Subramanian Iyer, Ph.D., Distinguished Chancellor’s Professor, Electrical Engineering Department, University of California, Los Angeles is scheduled to give the keynote presentation on the first day of the conference on “Packaging without the Package: A More Holistic Moore’s Law.” With the well-documented slowing down of scaling and the advent of the Internet of Things, there is a focus on heterogeneous integration and system-level scaling. Packaging itself is undergoing a transformation that focuses on overall system performance through integration rather than on packaging individual components. The University of California proposes ways in which this transformation can evolve to provide a significant value at the system level while providing a significantly lower barrier to entry compared with a chip-based SoC approach that is currently used. More importantly it will allow us to re-architect systems in a very significant way. This transformation is already under way with 3-D stacking of dies, Wafer level fan-out processing, and will evolve to make heterogeneous integration the backbone of a new SoC methodology, extending to integrate entire Systems on Wafers (SoWs). Professor Iyer will describe the technology his team uses and their results to-date. This has implications in redefining the memory hierarchy in conventional systems and in neuromorphic systems. These concepts are extended to flexible and biocompatible electronics with medical engineering applications.

Richard (Kwang Wook) Bae, Vice President, Corporate Strategy & Planning, Samsung Electro-Mechanics, will deliver the keynote on the second day, entitled “Samsung’s FOPLP: Beyond Moore.” Innovation and economics in semiconductor fabrication have followed Moore’s Law in past decades. However, as front-end processing is facing physical limits and the economic advantage described by Moore’s Law is fading, innovation in back-end processing has become critical. As the industry moves “Beyond Moore,” two questions come to mind: 1) What is the next-generation of packaging, and 2) What features should it have? Related to these topics are a discussion of the characteristics of the fan-out business and the advantage of Samsung’s fan-out panel-level packaging (FOPLP).

Han Byung Joon, Ph.D., Chief Executive Officer, STATS ChipPAC is scheduled to give the keynote presentation in the afternoon on the second day of the conference on “Innovative Packaging Technologies Usher in a New Era for Integration Solutions.” Rapidly evolving demands for greater system performance, increased functionality and reduced form factor are driving three key paradigm shifts in the industry. First, product miniaturization and the modularization of functionality is accelerating growth in system level integration. Second, increasing I/O densities and complex integration requirements in a smaller form factor are leading to a wide range of 2.5D and 3D fan-out wafer level packaging solutions. Third, Chinese fabless customers are requiring sophisticated packaging technologies to be competitive with the top international players. Dr. Han will discuss these important paradigm shifts and how wafer level technology is a key enabler for innovative integration solutions in smartphones, Internet of Things and wearable devices, data storage, networking and automotive electronics.